In CMOS circuits the absolute strength of a P-device or an N-device or the relative strength of a P-device to an N-device determines several characteristics of the circuit such as timing, drive strength, and rise/fall times. The absolute or relative strength of a P-device or of an N-device can drift due to the standard spread in manufacturing process tolerances or with time due to phenomena such as Negative Bias Thermal Instability (NBTI), Positive Bias Thermal Instability (PBTI), or Hot Carrier Injection (HCI).
In the prior art, the solution has been to provide a circuit that can handle such drift, by providing longer timing intervals, larger base drive strength, and longer times for capturing data dependent on rise/fall times. However, this type of overhead is costly.